Research on instruction scheduling for extended VLIW based on RISC-V compression instruction set

Abstract

In recent years, the Internet of Things (IoT) has become widespread across a broad range of systems. Embedded processors used in such IoT devices have tight constraints on area, energy budget, and other resources. As a processor architecture for embedded systems, Very Long Instruction Word (VLIW) is one of the useful methods for implementing embedded systems. In VLIW processors, a dedicated compiler statically schedules instructions according to the design, thereby achieving high Instruction Level Parallelism (ILP) without requiring a complex internal structure. In addition, the RISC-V compressed instructions set are well suited to embedded processors. However, compressed instructions have the problem that they must be used in combination with basic instructions. To solve the problem, a translator that converts basic instructions to compressed instruction has been proposed. Furthermore, a VLIW processor focusing on compressed instructions have also been proposed, with parameterizable numbers of functional units (e.g., ALUs). However, there is no VLIW compiler for RISC-V compression instructions, so instruction schedules must still be managed manually to use the processor. Furthermore, because this VLIW architecture supports varying the number of functional units via a configuration file for automated design, the scheduler must adapt its scheduling decisions to the VLIW configuration. To address the lack of a VLIW compiler supporting the RISCV compressed instruction and the need to perform instruction scheduling for VLIW architectures whose configurations vary according to a configuration file, we propose a VLIW instruction scheduler for the RISC-V compressed instruction that supports configuration file defined VLIW architectures, and we validate its functional correctness and evaluate its performance. As a result, we verified that the scheduler performs correctly under varying VLIW configurations and operates with low overhead relative to hand scheduling.